This invention relates to a gate drive circuit used for the voltage-driven semiconductor elements used in a power converter and to a power converting apparatus.
In a power converting apparatus such as an inverter or a converter which uses switching elements of voltage-driven type including insulated gate bipolar transistors (IGBTs) or power MOSFETs, electric energy is transferred from the input side to the output side by supplying and interrupting the voltage applied between the emitter and the gate of each switching element, e.g. IGBT. When the switching element is turned on or off, switching loss is incurred. This switching loss can be reduced by enhancing the gating drive efficiency and switching over between the conductive and cut-off states of the switching element swiftly. On the other hand, if the collector voltage of the IGBT (in the cut-off state) rises steeply due to the swift switching of the IGBT, the gate-emitter capacitance Cge is charged through the gate-collector capacitance Cgc. Consequently, the gate voltage is elevated, and if it exceeds a threshold, the IGBT fires erroneously. In order to reduce the switching loss due to the increase in switching speed and to prevent erroneous firing, a negative voltage is usually applied to the gate of the IGBT so as to prevent the gate voltage from rising due to the swift withdrawal of gate charges and the increase in the time rate of change dv/dt of the collector voltage.
JP-A-2009-21823 discloses a gate drive circuit which can apply a negative voltage to the gate of a semiconductor element by using a single power supply. The circuit configuration of the gate drive circuit, as shown in FIG. 1 attached to the disclosure, comprises a DC power supply Vdd, five switches SW1˜SW5, and a capacitor Cin. One terminal of the switch SW1 is connected with the positive terminal of the power supply Vdd; the switch SW2 is connected between the other terminal of the switch SW1 and the negative terminal of the power supply Vdd; one terminal of the switch SW3 is connected with the positive terminal of the power supply Vdd; the switch SW4 is connected between the other terminal of the switch SW3 and the switch SW5; the switch SW5 is connected between the other terminal of the switch SW4 and the negative terminal of the power supply Vdd; the capacitor Cin is connected between the other terminal of the switch SW1 and the other terminal of the switch SW4; the other terminal of the switch SW3 is connected with the gate of the power MOSFET; and the source of the power MOSFET is connected with the negative terminal of the power supply Vdd.
The operation of this circuit is described below. With SW1, SW3 and SW5 closed and with SW2 and SW 4 open, the gate voltage of the power MOSFET is elevated up to Vdd via SW3. On the other hand, the capacitor Cin is charged up to Vdd through a path consisting of SW1, Cin and SW5. Then, when SW1, SW3 and SW5 are opened and when SW2 and SW4 are closed, the gate of the power MOSFET is kept at a negative voltage (−Vdd) through a path consisting of SW4, Cin and SW2. In this way, a positive voltage and a negative voltage are applied in turn so that high speed turn-off can be effectuated and that erroneous firing can be prevented.
JP-A-2007-336694 discloses a gate drive circuit which can apply a negative voltage to the gate of an insulated gate type semiconductor device by using a single DC power source. The circuit configuration of the gate drive circuit, as shown in FIG. 1 attached to the disclosure, is as follows. A series circuit of transistors Q1 and Q2 is connected between the positive and negative electrodes of the DC power source VD; one end of a parallel circuit of a resistor R1 and a capacitor C1 is connected to the junction point of the transistors Q1 and Q2; one end of a gate resistor RG is connected to the other end of the parallel circuit; and the other end of the gate resistor RG is connected with the gate of the insulated gate type semiconductor element. A series circuit of a zener diode ZD1 and a reverse-flow preventing diode D1 is connected between the gate and the emitter of the insulated gate type semiconductor element PT. The operation of this circuit is as follows. When Q1 is turned on and Q2 is turned off, C1 functions as a differentiating circuit immediately after the turn-on of Q1. Accordingly, spike current flows through a path consisting of C1, RG and the gate-emitter capacitance of PT. A voltage clamped by ZD1 is applied to the gate of PT. While PT is conductive, the clamped voltage is equal to VD−VC1, VC1 being the voltage developed across C1. Then, when Q1 is turned off and Q2 is turned on, C1 is charged to develop a voltage of VD−Vz. As a result, a negative voltage is applied to the gate of PT. Hence, high speed turn-off can be effectuated and turn-off loss can also be reduced.